1. Field of the Disclosed Embodiments
The present invention relates generally to high-resolution time-to-digital converter (TDC) and more particularly to a method and apparatus for exploiting process mismatch to improve resolution.
2. Introduction
Many electronic devices operate off a periodic clock signal to synchronize the transmission of data between electronic components within the device. Periodic clock signals can be provided by an oscillator, such as voltage controlled oscillator (VCO/DCO) or digitally controlled oscillator (DCO). Periodic clock signals are also used in radio devices and wireless devices to generate specified frequencies that can be used for a variety of purposes including upconversion, downconversion, and transmission on a carrier frequency. A wireless communication device may be allocated a specified range of frequency bands in which data is transmitted. A VCO/DCO can be used in a phase-locked loop (PLL) to generate various frequency bands. A time-to-digital converter (TDC) can be used in a phase-locked loop (PLL) to lock the frequency of the VCO/DCO to specified frequency.
A wireless communication device for emerging gigabit per second wireless standards require local oscillator (LO) signals with very good spectral purity. Digital fractional-n PLLs are an attractive choice for LO generation in high performance radio transceivers on account of the small area, ease of porting, PVT (process, voltage and temperature) insensitive loop dynamics and scan programmability/re-configurability. The resolution and linearity of the Time-Digital Converter (TDC) limit the spectral purity achievable with a digital fractional-n PLL. As an example, a fractional-n PLL for the 5 GHz band requires the TDC to span a dynamic range of two hundred picoseconds (ps). At the same time, the TDC resolution and non-linearity are required to be better than 1 ps in order to meet the phase noise and spur requirements of the Gbps standards.
A conventional digital PLL achieves a sub-gate delay TDC resolution through the use of techniques such as delay verniers or delay interpolation. Mismatch and variations along the TDC delay line can introduce non-linearity and non-monotonicity in the TDC behavior, effectively degrading the PLL performance. The TDC delay cells will have to be sized up to reduce mismatch and variations. Consequently, the power dissipation increases quadratically with resolution, rendering the design impractical.